FPGA simulated annealing accelerator
US8296120B2 · kind B2 · utility
12Cited by
10References
10Claims
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Key dates
| Filing date | Jun 22, 2009 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Apr 26, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Iterative repair problems are generally solved using a combinatorial search method such as simulated annealing are addressed with a FPGA-based coarse-grain pipelined architecture to accelerate a simulated annealing based iterative repair-type event scheduling application. Over 99% of the work done by any simulated annealing algorithm is the repeated execution of three high-level steps: (1) generating, (2) evaluating, and (3) determining the acceptability of a new problem solution. A pipelined processor is designed to take advantage of these steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.