Patent · US Active

SAT-based synthesis of a clock gating function

US8296256B2 · kind B2 · utility

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0References

18Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Eli Arbel · Migdal HaEmek, IL
Oleg Rokhlenko · Haifa, IL
Karen Frida Yorav · Haifa, IL

Key dates

Filing date	Oct 15, 2009
Grant date	Oct 23, 2012
Priority date	—
Expiry date	Feb 27, 2031

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Clock gating circuit is determined by transforming a clock gating opportunity function to a non-Boolean function and constraining inputs of the non-Boolean function. The non-Boolean function may be a ternary function. Constraining the inputs may be achieved by introducing control variables and a cardinality constraint associated with their values. The non-Boolean function may be utilized to approximate universal quantification of an input assigned with a non-Boolean value, such as “don't care” value. The non-Boolean function may be utilized to provide an ALL SAT solution of a Boolean function using a SAT solver.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.