Methods and systems for microcode patching
US8296528B2 · kind B2 · utility
19Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2008 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Jun 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for performing microcode patching are presented. In one embodiment, a data processing system comprises a cache memory and a processor. The cache memory comprises a plurality of cache sections. The processor sequesters one or more cache sections of the cache memory and stores processor microcode therein. In one embodiment, the processor executes the microcode in the one or more cache sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.