Loading entries into a TLB in hardware via indirect TLB entries
US8296547B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2009 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Dec 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1009
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.