Codes for limited magnitude asymmetric errors in flash memories
US8296623B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2008 |
| Grant date | Oct 23, 2012 |
| Priority date | — |
| Expiry date | Apr 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Error correction is tailored for the use of an ECC for correcting asymmetric errors with low magnitude in a data device, with minimal modifications to the conventional data device architecture. The technique permits error correction and data recovery to be performed with reduced-size error correcting code alphabets. For particular cases, the technique can reduce the problem of constructing codes for correcting limited magnitude asymmetric errors to the problem of constructing codes for symmetric errors over small alphabets. Also described are speed up techniques for reaching target data levels more quickly, using more aggressive memory programming operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.