Routing layer for mitigating stress in a semiconductor die
US8299632B2 · kind B2 · utility
5Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2011 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Apr 22, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.