Level shift circuit and power conversion unit
US8299836B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2011 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Mar 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0175
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a level shift circuit, when a power-source voltage variation dV/dt of a high voltage side occurs and influences on a logic level of a circuit, the passing through of a malfunction signal is masked and prevented in the first and second logic circuits, by a signal from a time-constant generation circuit or a portion where a power voltage variation occurs in advance, by utilizing the fact that this variation occurs both at a set side and a reset side. When the power source voltage variation dV/dt is generated at a high voltage side, sufficient allowance in the timing of this masking prevents an erroneous signal from being transmitted to a flip-flop, and a control signal is transmitted from a low voltage side circuit not giving malfunction to a high voltage side circuit, even when there is a production variation in each element in semiconductor processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.