Semiconductor device and semiconductor memory device
US8300484B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2010 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Apr 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises a memory cell array including memory cells, a first bit line transmitting data stored in a selected memory cells, a single-ended first sense amplifier amplifying a signal voltage of the first bit line and converting the voltage into an output current, a second bit line selectively connected to the first bit line via the first sense amplifier, a second sense amplifier determining a level of the signal voltage, and a sense amplifier control circuit detecting a temperature of the memory cell array during an operation and controlling an end of an activation period of the first and/or second sense amplifiers in accordance with a detection result of the temperature. In the semiconductor device, the sense amplifier control circuit controls to delay the end of the activation period at least at a predetermined high temperature indicated by the detection result relative to at an ordinary temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.