Semiconductor memory and system
US8300490B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 10, 2010 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Apr 30, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory includes a word line coupled to memory cells that transmits a word line signal; at least one word repeater circuit that includes a first load circuit disposed on the word line; a first dummy word line disposed along the word line that transmits a first dummy word line signal; at least one dummy repeater circuit that includes a second load circuit disposed on the first dummy word line; bit lines coupled to the memory cells; column switches that couple the bit lines to data lines, respectively; a column selection line disposed along the word line that transmits a column selection signal for controlling each column switch; and at least one column repeater circuit disposed on the column selection line that outputs the column selection signal in synchronization with the first dummy word line signal input to the first dummy repeater circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.