Programmable packet processor with flow resolution logic
US8300534B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2010 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Dec 8, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/602
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A programmable packet switching controller has a packet buffer, a programmable packet classification engine and an application engine. The packet buffer stores inbound packets, and includes a header data extractor to extract header data from the inbound packets and store the extracted header data in a header data cache. The header data extractor also generates a header data cache index and provides it to the packet classification engine for it to retrieve the extracted header data. The application engine has a number of programmable sub-engines arrayed in a pipelined architecture. The packet classification engine provides start indicators based on the packet classification to the programmable sub-engines to identify application programs to be executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.