Power-saving method for Viterbi decoder and bit processing circuit of wireless receiver
US8300738B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 4, 2008 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Aug 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0054
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A power-saving method for Viterbi decoder and bit processing circuit of wireless receiver is provided. In response to various computational load of bit processing circuit and/or Viterbi decoder of a wireless receiver, the method is used for adjusting duty cycle of the bit processing circuit and/or the Viterbi decoder so as to save power in addition, in response to various data rates of the wireless receiver, the Viterbi decoder and the bit processing circuit are provided with power based on various duty cycles of related time pulse signals, thereby preventing the Viterbi decoder and/or the bit processing circuit from consuming power while being idle (during time segments of idle operation), so as to reduce power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.