Method and apparatus for generating soft bit values in reduced-state equalizers
US8300739B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 21, 2009 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Aug 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4146
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A demodulator is provided that functions as a reduced-state equalizer and produces reliable soft bit values. According to an embodiment, soft bit values are generated for a sequence of transmitted symbols using a demodulator by updating an M-state trellis managed by the demodulator responsive to a transition from symbol time n−1 to symbol time n, where M is a function of the number of bits per symbol in the sequence of transmitted symbols. Survivor metrics associated with the M states of the trellis are saved each symbol time so that the demodulator can calculate soft bit values with regard to transitions from symbol time n+D−1 to symbol time n+D. The survivor metrics indicate the probability that each respective state represents the transmitted symbol associated with symbol time n+D−1. The trellis is traced back through to calculate soft bit values for a symbol detected at symbol time n−D based on survivor metrics saved for the M states at symbol time n−D.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.