Clock and data recovery with a data aligner
US8300754B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2009 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Jun 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method includes receiving first and second input streams comprising first and second input data bits, respectively. The method includes generating first and second recovered clocks based on the first and second input streams, respectively. The method includes retiming and demultiplexing the first and second input data bits to generate n first recovered streams and n second recovered streams, respectively, each comprising first and second recovered data bits, respectively. The method further includes determining a phase difference between the first and second recovered clocks; aligning the first recovered data bits with the second recovered data bits based at least in part on a value of n and the phase difference; combining the first and second recovered data bits to generate an output stream; and retiming the first and second recovered data bits in the output stream based on either the first or second recovered clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.