Patent · US Active

Direct memory access for advanced high speed bus

US8301820B2 · kind B2 · utility

0Cited by

6References

19Claims

0Family size

Assignee

STMicroelectronics Belgium · BE

Inventor

Rudolph Alexandre · Saint-Josse-ten-Noode - Sint-Joost-ten-Node, BE

Key dates

Filing date	Jun 12, 2009
Grant date	Oct 30, 2012
Priority date	—
Expiry date	Jun 8, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/28
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory system for use with a master-slave type bus such as an AHB bus has a memory, a bus interface to allow memory access from the bus, and a direct memory access interface to allow memory access from a DMA controller without occupying the bus. The system can reduce occupancy of the bus, it can allow dedicated DMA access protocols faster than the bus protocol to be used, and can remove or reduce the need for bus arbitration and associated circuitry and delays. An arbiter can arbitrate between the memory accesses and give priority to DMA accesses.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.