Secondary core ONU to OLT via internal EPON bus coupled multi-core processor for integrated modular avionic system
US8301867B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2009 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Feb 17, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-core processor system including a main processor, an internal EPON bus, and a plurality of secondary core processors. The main processor includes a processing unit; an offload engine operatively connected to the processing unit for routing data to and from the processing unit; a plurality of main processor optical network units (ONU's) operatively connected to the offload engine; and, a dual optical line terminal (OLT) operatively connected to the offload engine. The internal EPON bus is operatively connected to the OLT. The plurality of secondary core processors are located physically separate from the main processor, each secondary core processor having a respective secondary core processor ONU being operatively connected to the main processor via the internal EPON bus. A number of the multi-core processor systems can be used to form an integrated modular avionics (IMA) system when operatively connected to remote data concentration components via an external EPON bus connected to the dual OLTs of the multi-core processor systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.