Multi-clock asynchronous logic circuits
US8301933B2 · kind B2 · utility
7Cited by
7References
28Claims
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Key dates
| Filing date | Sep 14, 2009 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Jan 31, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and circuits for implementing multi-clock designs in asynchronous logic circuits are described. A method may include associating one or more data tokens with a clock domain of a multi-clock domain netlist. A durational relationship between a clock period associated with the clock domain and one or more other clock domains of the multi-clock domain netlist may be determined. Data tokens used in other clock domains may be transformed based on the determined relationship.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.