Interleaving scheme for an LDPC coded 32 APSK system
US8301960B2 · kind B2 · utility
1Cited by
12References
2Claims
0Family size
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Key dates
| Filing date | Feb 22, 2010 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Nov 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2053
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An approach is provided for interleaving low density parity check (LDPC) encoded bits in 32APSK modulation systems. By assigning the bits determining modulation symbols based on different bit degrees, one can efficiently find the desirable tradeoff between error performance and error floor provided by the LDPC codes in use.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.