System and method of decoding data with reduced power consumption
US8301987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2009 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Jan 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoder is disclosed that can reduce power consumption at different stages of a decoding process. At a first stage where the decoder calculates residual values, the decoder can reduce power consumption by calculating residual values using less than a full set of division circuits. A reduced number of division circuits may be sufficient to successfully calculate residuals associated with the codeword to complete the decoding process. Division circuits that are not used may be disabled to reduce power consumption. At another stage of the decoding process where the decoder generates coefficients that are used to identify locations of errors in the codeword, the decoding process can limit power consumption by reducing the number of iterations of a polynomial generator by incorporating termination decision circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.