Programmable compute unit with internal register and bit FIFO for executing Viterbi code
US8301990B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2007 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Mar 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4169
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable compute unit with an internal register with a bit FIFO for executing Viterbi code is configured to accumulate in the forward path the best-path to each state in an internal register and store the survivor trace back information bit for each state in each stage in a bit FIFO; and in the trace back, selecting the optimal best-path through the Viterbi trellis by tracing through the bit trace back information survivor bits beginning with the survivor bit of the last stage path; and generating in response to the Viterbi constrain length and a current bit FIFO address, the next bit FIFO address and decoded output bit for the next previous stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.