System and apparatus for error-correcting register files
US8301992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2009 |
| Grant date | Oct 30, 2012 |
| Priority date | — |
| Expiry date | Mar 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and computer program product for enabling a register file to recover from detection of a parity error. A first register file and a second register file are associated with a parallel file structure. When the parity error is detected, the system determines whether the first register file or second register file is associated with the parity error. The register file determined to have the parity error is associated with an offending register and a non-offending register is associated with the “good” register file. Subsequent to the detection of the parity error, the system executes a repair sequence, whereby the register file associated with the offending register receives data from the register file associated with the non-offending register. The offending register file recovers from the parity error with or without the use of a parity interrupt.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.