Patent · US Active

Verification of logic circuit designs using dynamic clock gating

US8302043B2 · kind B2 · utility

2Cited by

8References

15Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Christian Habermann · Stuttgart, DE
Christian Jacobi · West Park, US
Matthias Pflanz · Schenefeld, DE
Hans-Werner Tast · Holzgerlingen, DE
Ralf Winkelmann · Eppelheim, DE

Key dates

Filing date	Sep 7, 2010
Grant date	Oct 30, 2012
Priority date	—
Expiry date	Dec 8, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/06
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method and system for verifying a logic circuit design using dynamic clock gating is disclosed. The method comprises choosing at least one master seed to determine initial values as initialization for said logic circuit and/or stimuli data for at least one interface of said logic circuit, choosing at least two different dynamic clock gating configurations for every chosen master seed, executing a functional simulation with said logic circuit for every chosen dynamic clock gating configuration by using said determined initialization and/or stimuli data based on a corresponding master seed, comparing simulation results of functional simulations against each other executed with said logic circuit for at least two different chosen dynamic clock gating configurations, and reporting an error if said at least two simulation results are not identical.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.