Patent · US Active

Method and system for placement of electronic circuit components in integrated circuit design

US8302056B2 · kind B2 · utility

6Cited by

1References

11Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Elmar Gaugler · Eppelheim, DE
Wilhelm Haller · Winnenden, DE
Friedhelm Kessler · Eppelheim, DE

Key dates

Filing date	Jul 7, 2010
Grant date	Oct 30, 2012
Priority date	—
Expiry date	Aug 29, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/392
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The invention relates to a method and a system for placing macros of a multilevel hierarchical description of a design unit on a chip. The method starts off by repartitioning the macro structure of the design unit into a set of latch macros and a set of combinatorial macros. By definition, a combinatorial macro is constructed in such a way that it contains no latches, and a latch macro contains latches and is constructed in such a way that each primary input/output of the latch macro coincides with an input or an output of a latch within said latch macro. After repartitioning the macro structure, the latch macros are synthesized within temporary boundaries and placed on the chip. Subsequently, the combinatorial macros are sequentially placed within a temporary boundary and synthesized one by one.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.