Structure and method for fabrication of field effect transistor gates with or without field plates

US8304332B2 · kind B2 · utility

Assignee

• BAE Systems Information and Electronic Systems Integration Inc. · US

Inventors

• Anthony A. Immorlica · Manlius, US
• Pane-chane Chao · Nashua, US
• Kanin Chu · Nashua, US

Key dates

• Filing date: Jun 1, 2011
• Grant date: Nov 6, 2012
• Expiry date: Jun 1, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/8503

Abstract

A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.