Active device array substrate
US8304770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2009 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Apr 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An active device array substrate including a first patterned conductive layer, a dielectric layer, a second patterned conductive layer, a passivation layer and pixel electrodes is provided. The first patterned conductive layer includes scan lines, common lines, gates and strip floating shielding patterns. The dielectric layer covering the first patterned conductive layer has first contact holes which expose a portion of the common lines, respectively. The second patterned conductive layer includes data lines, sources, drains and strip capacitance electrodes. Each strip capacitance electrode is electrically connected to one of the common lines through one of the first contact holes. A gap is formed between each data line and one strip capacitance electrode, and the strip floating shielding patterns are disposed under the data lines, the gap and the strip capacitance electrodes. Each pixel electrode is electrically connected to one of the drains through one of the second contact holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.