Printed dopant layers
US8304780B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2010 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Aug 31, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02318
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.