Semiconductor device having a multilevel interconnect structure and method for fabricating the same
US8304908B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Mar 19, 2009 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Jul 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilevel interconnect structure in a semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.