Flop type selection for very large scale integrated circuits
US8305126B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2011 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | May 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.