Memory/logic conjugate system
US8305789B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Dec 23, 2010 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | May 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.