Patent · US Active

Integrated circuit with an array of resistance changing memory cells

US8305793B2 · kind B2 · utility

24Cited by

1References

20Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Petra Majewski · Munich, DE
Jan Boris Philipp · Peekskill, US

Key dates

Filing date	May 16, 2008
Grant date	Nov 6, 2012
Priority date	—
Expiry date	Sep 7, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG11C2213/32
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit includes an array of resistance changing memory cells, and a circuit configured to apply an initialization signal to a first one of the memory cells that is in a virgin resistance state. The initialization signal is configured to modify the first memory cell without switching an operation state of the first memory cell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.