Memory control with selective retention
US8305828B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 30, 2010 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Aug 30, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a memory circuit and a method of controlling data retention in the memory circuit, wherein a supply signal is selectively switched to a respective one of at least two virtual supply lines (24) each shared by a respective one of a plurality of groups (30-1 to 30-n) of memory cells (C0,0 to Cy,z). The selective switching is controlled based on a global activity control signal (A), used for setting the memory circuit either into a standby state or into an active state, and a local data retention indication signal (DR1 to DRn) allocated to a dedicated group of memory cells. Thereby, the data retention part of the memory circuit can be adapted to the application and its state, and standby mode leakaged power is only dissipated in those memory cells for which data retentions actually required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.