System and method to improve sequential serial attached small computer system interface storage device performance
US8307128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2006 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Sep 6, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, computer-implementable method, and computer-readable medium for improving sequential serial attached small computer system interface storage device performance. According to a preferred embodiment, a microprocessor within a target device receives a collection of tasks from at least one initiator device via a collection of initiator paths. The target device is a cyclic non-volatile memory medium. The microprocessor queues the collection of tasks according to a collection of task list. Each task list corresponds to a respective initiator path. The microprocessor combines the collection of tasks in an execution queue. The collection of tasks on the execution queue is reordered based on a priority scheme. The microprocessor executes the collection of tasks from the execution queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.