Page fault handling in a virtualized computer system
US8307191B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 2008 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Jun 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/151
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to page fault handling in a virtualized computer system in which at least one guest page table maps virtual addresses to guest physical addresses, some of which are backed by machine addresses, and wherein at least one shadow page table and at least one translation look-aside buffer map the virtual addresses to the corresponding machine addresses. Indicators are maintained in entries of at least one shadow page table, wherein each indicator denotes a state of its associated entry from a group of states consisting of: a first state and a second state. An enhanced virtualization layer processes hardware page faults. States of shadow page table entries corresponding to hardware page faults are determined. Responsive to a shadow page table entry corresponding to a hardware page fault being in the first state, that page fault is delivered to a guest operating system for processing without activating a virtualization software component. On the other hand, responsive to a shadow page table entry corresponding to a hardware page fault being in the second state, that page fault is delivered to a virtualization software component for processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.