Short-circuit evaluation of Boolean expression by rolling up sub-expression result in registers storing default value
US8307197B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 2, 2009 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Jun 9, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor including a Boolean logic unit, wherein the Boolean logic unit is operated for performing the short-circuit evaluation of a Normal Form Boolean expression/operation, a plurality of input/output interfaces in communication with the Boolean logic unit, wherein the plurality of input/output interfaces are operated for receiving a plurality of compiled Boolean expressions/operations and transmitting a plurality of compiled results, and a plurality of registers coupled to the plurality of input/output interface circuits, wherein the plurality of multi-bit registers include an instruction register, a first address register and a second address register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.