Scalable decoder architecture for low density parity check codes
US8307255B2 · kind B2 · utility
2Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2009 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Jan 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6505
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A layered message updating method and system for the decoding of LDPC codes with high sub-matrix degree has a scalable and flexible decoder architecture to support LDPC codes with arbitrary high sub-matrix degree with very small hardware overhead and high throughput. Embodiments of the invention support LDPC codes with sub-matrix degree W>=1. The architecture does not require duplication of extrinsic memory which greatly reduces decoder complexity. The size of the memory is also independent of sub-matrix degree which makes the decoder scalable for large W values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.