Method for dummy metal and dummy via insertion
US8307321B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2010 |
| Grant date | Nov 6, 2012 |
| Priority date | — |
| Expiry date | Nov 26, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for dummy metal and dummy via insertion is provided. In one embodiment, dummy metals are inserted using a place and route tool, where the place and route tool has timing-awareness. Then, dummy vias arrays are inserted inside an overlap area of dummy metals using a design-rule-checking utility. Fine-grained dummy vias arrays are inserted in available space far away from main patterns. The dummy-patterns resulting from the inserted dummy vias are compressed using the design-rule-checking utility to reduce the size of a graphic data system file generated from the integrated circuit design. The dummy vias can be inserted with relaxed via spacing rules. The dummy metals are inserted with a constant line-end spacing between them for better process control and the maximum length of the dummy metal can be limited for smaller coupling effects. The dummy vias can have various sizes and a square or rectangular shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.