Method for modeling devices in a wafer
US8307539B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2009 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Aug 12, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49041
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for modeling devices in a wafer comprises the step of providing the wafer comprising a first plurality of devices having a track width and a first stripe height, a second plurality of devices having the track width and a second stripe height, and a third plurality of devices having the track width and a third stripe height. The method further comprises the steps of measuring resistance values for the first, second and third plurality of devices to obtain a data set correlating a stripe height and a resistance value for each of the first, second and third plurality of devices, and estimating a linear relationship between resistance and inverse stripe height for the first, second and third plurality of devices based on the data set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.