Assembly, chip and method of operating
US8310024B2 · kind B2 · utility
3Cited by
4References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 2007 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Jun 23, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The chip comprises a network of trench capacitors and an inductor, wherein the trench capacitors are coupled in parallel with a pattern of interconnects that is designed so as to limit generation of eddy current induced by the inductor in the interconnects. This allows the use of the chip as a portion of a DC-DC converter, that is integrated in an assembly of a first chip and this—second chip. The inductor of this integrated DC-DC converter may be defined elsewhere within the assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.