Anti-arcing circuit for current-fed parallel resonant inverter
US8310160B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2009 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Apr 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05B41/2855
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An arc protection circuit is provided for a current-fed, parallel-resonant inverter ballast, the circuit having a lamp signal sensing circuit coupled across one or more lamps and designed to detect a signal through the lamps, a shutdown circuit coupled to the sensing circuit and operable to disable the ballast in response to a disturbance such as an arc in the detected signal, at least a portion of the shutdown circuit defining a first time delay from detection of the disturbance in the signal during which the ballast operates normally, and after which the ballast may be disabled in response to the disturbance; and an automatic restart circuit coupled to the shutdown circuit and operable to enable restarting of the ballast, at least a portion of the restart circuit defining a second time delay during which the ballast remains disabled, after which the ballast may be restarted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.