ADC having improved sample clock jitter performance
US8310290B2 · kind B2 · utility
4Cited by
4References
6Claims
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Key dates
| Filing date | Nov 2, 2010 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Jun 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In conventional analog-to-digital converter (ADC) systems, jitter can be a problem because of delay circuits within the sample signal path. Here, an ADC system is provided with a modified delay locked loop (DLL), namely having a variable delay and a fixed delay. The modification to the delay line of DLL enables the removal of delay circuits from the sample path, improve the overall signal to noise ration (SNR).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.