Broadcast receiver system
US8310601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2009 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Jun 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/414
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An interface circuit configured to connect between (a) a broadcast receiver tuner and associated circuitry for the receiving and processing of broadcast radio frequency signals, and (b) a general purpose computer device programmed with software demodulation code configured to engage a general purpose processor in signal demodulation functions, the interface circuit comprising: a data interface comprising a packetisation buffer connected to receive (i) digital signal sample data from a signal path of the tuner and associated circuitry and (ii) indications of control settings which are applied to one or more configurable components during taking of the sample data, said packetisation buffer being operable to construct packets comprising blocks of sample data and header information carrying said control settings indications; a control interface configured to receive control instructions from tuner control code running on the general purpose computer device; and a microcontroller operable to receive the control instructions from the control interface and distribute corresponding control settings to configurable components of the tuner and associated circuitry, said microcontroller also…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.