Semiconductor memory device having balancing capacitors
US8310859B2 · kind B2 · utility
1Cited by
7References
7Claims
0Family size
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Key dates
| Filing date | Sep 30, 2009 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Nov 8, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.