Speed-level calculator and calculating method for dynamic voltage scaling
US8312070B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2008 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Sep 15, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is directed to a speed-level calculator and calculating method for dynamic voltage scaling. The speed-level calculator comprises a deadline counter, a shifter, and a fixed-point multiplier. The deadline counter calculates the residual time D from current time to each task deadline for completing an episode. The shifter generates a D′ value by shifting the D value to the right for e-m bits, and takes the decimal fraction part of the D′ value for m bits. The speed-level calculator further comprises a saturation control circuit to detect if an overflow occurs on the D′ value. According to a pre-calculated parameter αi corresponding to each task Ti, the fixed-point multiplier performs the multiplication of D′ and αi. After completing saturation and rounding on the multiplication result, a corresponding clock period is generated by taking the integer part. This clock period is used as speed-level to switch the processor voltage and frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.