Virtual machine access to storage via a multi-queue IO storage adapter with optimized cache affinity and PCPU load balancing
US8312175B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2010 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | May 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45579
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for use in a system that includes a host machine that includes multiple physical CPUs (PCPUs) and at least two cache nodes that are shared by different sets of the PCPUs, comprising: creating in a memory device multiple sets of lanes each lane set associated with a respective PCPU set; tracking levels of processing activity of the PCPUs of each PCPU set; using an MSIX vector value to associate lanes with PCPUs; receiving a IO request from any given PCPU from among the multiple PCPUs; and assigning the IO request to a respective lane based at least in part upon the PCPU set associated with the lane and PCPU processing activity levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.