Power management for systems on a chip
US8312305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2010 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Mar 11, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for controlling a multitasking microprocessor system includes an interconnect, a plurality of processing units connected to the interconnect forming a single-source, single-sink flow network, wherein the plurality of processing units pass data between one another from the single-source to the single-sink, and a monitor connected to the interconnect for monitoring a portion of a resource consumed by each of the plurality of processing units and for controlling the plurality of processing units according to a predetermined budget for the resource to control a data overflow condition, wherein the monitor controls performance and power modes of the plurality of processing units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.