Determining data transmission error and/or checking or confirming such error determinations
US8312362B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 4, 2008 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Jan 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data partitioning circuit partitions received data and an appended error checking code into a plurality of data lines having a fixed length and a last line. A vector selector inserts a pad vector after the appended error checking code when the last line is less than the first length and not equal to the first fixed length minus a length of the appended error checking code, and selects one of a plurality of error checking vectors, the pad vector having a length providing the last line with the first fixed length when appended thereafter, and the plurality of error checking vectors comprising an initial vector and an error checking code feedback vector. An error checking code calculation circuit performs error checking calculations on the plurality of data lines and the last line to generate an error checking result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.