Method and system for generating partitioned matrices for parallel circuit simulation
US8312399B2 · kind B2 · utility
3Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2009 |
| Grant date | Nov 13, 2012 |
| Priority date | — |
| Expiry date | Aug 30, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Over the years, parallel processing has become increasingly common. Conventional circuit simulators have not taken full advantage of these developments, however. Here, a circuit simulator and system are provided that partitions circuit matrices to allow for more efficient parallel processing to take place. By doing this, the overall speed and reliability of the circuit simulator can be increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.