Frequency divider for generating output clock signal with duty cycle different from duty cycle of input clock signal
US8314639B2 · kind B2 · utility
2Cited by
12References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2010 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Apr 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency divider includes a plurality of logic circuit blocks. Each of the logic circuit blocks has a plurality of control terminals. At least one of the control terminals of one of the logic circuit blocks is arranged to receive an input clock signal having a first duty cycle. At least one of the remaining control terminals of the one of the logic circuit blocks is arranged to couple another one of the logic circuit blocks by a positive feedback. A clock signal at the at least one of the remaining control terminals has a second duty cycle different from the first duty cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.