Memory controllers
US8315114B2 · kind B2 · utility
2Cited by
2References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 25, 2010 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Jun 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques pertaining the designs of memory controller are disclosed. According to one aspect of the present invention, a memory controller reduces delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller thereof. In one embodiment, the memory controller employs four IO ports, two inverters, six edge triggers and a multiplexer. By feeding back an inverted clock signal and utilizing the rising and filing edges of the clock signal, the delays in a data strobe signal of a DDR memory relative to a clock signal of a memory controller are considerably reduced or minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.