Multi-chip package semiconductor memory device providing active termination control
US8315122B2 · kind B2 · utility
9Cited by
1References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2010 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Jan 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1057
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a multi-chip package structure providing active termination control. The semiconductor memory device includes first and second memory chips sharing a data I/O bus. The first memory chip includes a first chip enable (CE) port determining whether the first memory chip is activated, and a second CE port monitoring whether the second memory chip is activated. An active termination unit is turned ON only when the first and second chips are deactivated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.