Enhancement of transition region equalization in a decision feedback equalizer
US8315300B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 2009 |
| Grant date | Nov 20, 2012 |
| Priority date | — |
| Expiry date | Jan 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03579
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A decision feedback equalizer includes an input path for receiving a bitstream with inter-symbol interference, and a feedback signal path is coupled to the input path for correcting a sampled value of an incoming bit of the bitstream based on inter-symbol interference of a preceding bit. The feedback signal path includes a controllable delay circuit for receiving the preceding bit. A feedback path controller is coupled to the controllable delay circuit to regulate a delay introduced to the preceding bit. The delay is a function of an accumulated value of data of early-late events of a sampling instant of the bitstream for different data pulse patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.